1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device including transistors of an SOI (Silicon On Insulator) structure formed on an insulating film. Specifically, the present invention relates to an arrangement of a memory cell array in a multiport semiconductor memory device that can be accessed via multiple ports.
2. Description of the Background Art
In fields of image data processing and the like, system LSIs in which a logic such as a processor and a memory device are integrated on a single semiconductor chip have been widely used for high-speed processing of a large amount of data. In these system LSIs, the logic and the memory device are interconnected via on-chip interconnection lines, so that the following advantages can be achieved.
(1) A load on a signal line is smaller than that on an on-board interconnection line, and data and signals can be transmitted fast.
(2) Since the number of pin terminals is not restricted, a data bus width can be increased, and a band width of data transfer can be increased.
(3) Since various components are integrated on the semiconductor chip, a small-size and light system can be achieved.
(4) Macros prepared in a library can be arranged as components to be formed on the semiconductor chip, so that design efficiency is improved.
For the above reasons, the system LSIs have been widely used in various fields. For the integrated memory devices, the system LSIs employs, e.g., a Dynamic Random Access Memory (DRAM), an Static Random Access Memory (SRAM) and a nonvolatile semiconductor memory device such as a flash memory. For the logics, the system LSI employs, e.g., a processor performing control and data processing, an analog processing circuit such as an analog-to-digital converter circuit and the like, and a logic circuit performing dedicated logical processing.
The memory devices include a dual-port RAM that has two ports each allowing individual access for realizing a fast-access memory system. The dual-port RAM allows write/read of data via one of the access ports while data is being read or written via the other access port.
A dual-port RAM based on an SRAM cell has been widely known. Memory capacities must be increased as a data processing amount increases. Therefore, the dual-portion RAM based on the DRAM memory cell has been developed as disclosed in an article 1 (H. Hidaka, et al., “A High-Density Dual-Port Memory Cell Operation and Array Architecture for ULSI DRAM's”, ISSCC, vol. 27, No. 4, 1992, pp. 610-617) and an article 2 (Y. Agata, et al., “An 8-ns Random Cycle Embedded RAM Macro With Dual-Port Interleaved DRAM Architecture (D2RAM)”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 35, No. 11, 2000, pp. 1668-1672).
In the dual-port RAM disclosed in the article 1, one memory cell is formed using one capacitor and two transistors. Bit lines of different ports are arranged alternately to each other for reducing noises due to capacitive coupling between the bit lines. Sense amplifiers are arranged on the opposite sides of the bit lines, and are coupled to divided and undivided bit lines. By utilizing imbalance of the bit line capacitances, a read voltage difference of memory cell data is produced, and the sense amplifiers on the opposite sides amplify data read onto the divided and undivided bit lines in parallel with each other.
In the article 1, a folded bit line structure is used, and a sense amplifier is arranged for each bit line pair so that memory cells may be arranged at a high density. Also, the bit lines of the different ports are arranged alternately to each other for improving a noise margin.
The structure disclosed in the article 2 (Y. Agata, et al., “An 8-ns Random Cycle Embedded RAM Macro With Dual-Port Interleaved DRAM Architecture (D2RAM)”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 35, No. 11, 2000, pp. 1668-1672) likewise uses two-transistor/one-capacitor DRAM cells. In the structure disclosed in the article 2, the memory cells are arranged to provide an open bit structure for reducing an arrangement pitch of the sense amplifiers to reducing the memory cell size. The bit lines for the different ports are arranged alternately to each other, and it is intended to reduce the inter-bit-line capacitive coupling noise by using the bit line of one of the ports as a shield line when the other port is being accessed.
In the structure disclosed in the article 2, the access is made alternately to the two ports, and an internal data transfer operation is pipelined, so that fast access may be achieved. Further, for achieving a fast write operation, data is written into the memory cell before a transfer operation, and sense and restore operations are performed after the data writing so the write time may be reduced.
A memory cell structure that reduces power consumption and achieves a fast operation is disclosed in an article 3 (F. Morishita, et al., “A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI”, Proc. CICC, 2005, pp. 435-438) and an article 4 (K. Arimoto, et al., “A Configurable Enhanced T2RAM Macro for System-Level Power Management Unified Memory”, Proc. VLSI Symp.).
In the structure disclosed in the article 3, a memory cell is formed of two SOI (Silicon On Insulator) transistors connected in series. A body region of one of the transistors is used as a storage node, and the other transistor is used as an access transistor. A threshold voltage of the transistor for data storage changes according to a potential of the body region. A source node of the data storage transistor is kept at a power supply voltage level. In a data read operation, a current flowing through the memory cell is sensed for performing the data reading.
In the memory cell structure disclosed in the article 3, capacitive coupling between the body region and the control electrode of the data storage transistor is utilized for performing the data writing.
In the structure disclosed in the article 4 (K. Arimoto, et al., “A Configurable Enhanced T2RAM Macro for System-Level Power Management Unified Memory”, Proc. VLSI Symp.), the access transistor and the data storage transistor for one memory cell. The data read operation is substantially the same as that disclosed in the article 3, but the data write operation utilizes a GIDL (Gate Induced Drain Leakage) current in addition to the capacitive coupling between the gate and body regions.
In the article 4, this GIDL current is utilized to increase the potential of the storage node nearly to the power supply voltage level.
In the structure disclosed in the article 4, a transistor having a control gate directly connected to a body region is used as a sense amplifier. By directly connecting the gate to the body region, it is intended to use the body effect to do a high-speed sensing of potential changes of a control electrode (bit line) of a sense transistor. Thus, the transistors each having the body region and the gate electrode mutually connected are cross-coupled to implement the sense amplifier. By using the cross-coupled sense amplifier, the sense amplifier is arranged for each bit line pair so that it may be used for both the writing and reading.
As the miniaturization of manufacturing process is further advanced, elements are miniaturized according to a scaling rule, and a power supply voltage is lowered. In a DRAM cell, data is read by sensing a difference (read voltage) between a bit line voltage and a reference voltage. The read voltage depends on a capacitance ratio between a bit line and a memory cell capacitor. For obtaining a sufficient read voltage, a capacitance value of the memory cell capacitor must be determined according to the bit line capacitance.
In the DRAM cell, therefore, the size of the transistor can be reduced according to the scaling rule, but the scaling of the capacitor is impossible. Therefore, a further complicated DRAM process is required for scaling the memory cell in the large-capacity, dual-port RAM of the DRAM cell type disclosed in the articles 1 and 2. For example, it is necessary to form a capacitor of a three-dimensional structure or to form a small roughness on a surface of a capacitor electrode. This results in a problem of further increase in process cost.
In the DRAM-cell-type, dual-port RAM cell, destructive read is performed, and thus data reading destroys storage data of the memory cell. Therefore, when the access is being performed to a memory cell via one port, the access via the one port must be kept until restoring of the data to this memory cell is completed. During this operation, it is necessary to inhibit the access to the same memory cell via the other access port. When the memory cell at the same address is simultaneously access via the two ports, for example, the stored charges in the memory cell capacitor of the DRAM cell disperse to the two ports, so that a read voltage lowers, and a read failure may occur. For preventing this, it is necessary to perform address arbitration for inhibiting the simultaneous access to the word line at the same address for the multiple ports.
Therefore, the access to the same address from the multiple ports is restricted, and efficient access cannot be performed. For avoiding such an address conflict, an external processor or an external logic is kept in a wait state, which lowers the processing efficiency.
In the memories disclosed in the articles 3 and 4, the memory cell is formed of the transistors connected in series so that the scaling of the memory cell size can follow the miniaturization in the manufacturing process. In these articles 3 and 4, consideration is given only to a single-port structure, and no consideration is given to multi-port structures such as a dual-port structure.
Particularly, in the memories (TTRAM; Twin-Transistor RAM) disclosed in the articles 3 and 4, a source node of the transistor for storage in the memory cell is fixed, e.g., to a power supply voltage level. The data is read by sensing the current flowing through a series connection of the storage transistor and the access transistor. Therefore, for arranging the access transistors for different ports relative to the transistor for the data storage, it is necessary to devise the arrangement of the transistors in the memory cell, so that read currents for the respective ports may be equal in magnitude to each other.
Particularly, in the memory cell layout disclosed in the article 3, an active region of the access transistor is arranged parallel to and overlaps in a planar layout with the bit line, and it is difficult in such layout to achieve the two-port structure. Thus, the transistor for data storage and the transistor for access arranged on one column are aligned to each other in a column direction so that it is difficult to arranged the access transistor having two ports symmetrically with respect to the transistor for data storage.